This disclosure relates generally to design for manufacturing, and more specifically to design for manufacturing of integrated circuits using an electrically driven optical proximity correction (EDOPC).
An optical proximity correction (OPC) is typically used in the design of integrated circuits to correct for discrepancies that exist between patterns on an initial mask layout and how these patterns print on a semiconductor wafer using optical lithography. A typical OPC operation involves fragmentation and subsequent distortion of mask features to ensure that structures printed on the wafer closely resemble target shapes embodied in the initial mask layout. In particular, upon receiving the initial mask layout, a typical OPC operation begins by generating assist features and sizing features up for etch bias. This is followed by fragmentation to generate edges which can be subsequently moved to generate the target shapes. A lithography simulation supported by optical and resist models is run to help determine the resist shapes. Edge placement errors between printed shapes and target shape features embodied in the initial mask layout are determined at a number of sites and used to determine the amount of edge movements of the shapes in the mask layout that are needed to reduce these errors. Essentially, edge placement error (EPE) is a metric of how much disturbance there is between the patterns in the initial mask layout and the output of the simulation. If there is a large amount of disturbance, then the OPC moves edges and shapes in initial mask layout appropriately to control the amount of EPE. Once the OPC has determined that the EPEs are in control, then an output mask layout is generated and transferred to a mask house for mask preparation.
There are several shortcomings associated with using this OPC methodology. One shortcoming is that this OPC methodology concentrates on maintaining the edges of the shapes by minimizing EPEs to obtain pattern fidelity between the initial mask layout and lithography simulation output (i.e., the layout that will be printed on the wafer), but this does not necessarily guarantee that electric characteristics of the shapes will be obtained. For example, current through a transistor is inversely proportional to gate length, whereas minimization of EPE leads to a linear control over gate length, suggesting that a non-rectangular shape may actually exhibit more accurate electrical behavior. This inability to guarantee ideal electrical behavior characteristics affects parametric yield during manufacturing. Another shortcoming is that a large amount of computational effort is spent in correcting for corners and other regions which are electrically non-critical and may be only be important from a catastrophic yield point of view (e.g., opens, shorts, etc.).